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PIC18F66K80 FAMILY

DS39977F-page 200

2010-2012 Microchip Technology Inc.

12.5

Carrier Source Polarity Select

The signal provided from any selected input source for

the carrier high and carrier low signals can be inverted.

Inverting the signal for the carrier high source is

enabled by setting the MDCHPOL bit of the MDCARH

enabled by setting the MDCLPOL bit of the MDCARL

12.6

Carrier Source Pin Disable

Some peripherals assert control over their correspond-

ing output pin when they are enabled. For example,

when the CCP1 module is enabled, the output of CCP1

is connected to the CCP1 pin.

This default connection to a pin can be disabled by

setting the MDCHODIS bit in the MDCARH register for

the carrier high source and the MDCLODIS bit in the

MDCARL register for the carrier low source.

12.7

Programmable Modulator Data

The MDBIT of the MDCON register can be selected as

the source for the modulator signal. This gives the user

the ability to program the value used for modulation.

12.8

Modulator Source Pin Disable

The modulator source default connection to a pin can

be disabled by setting the MDSODIS bit in the MDSRC

12.9

Modulated Output Polarity

The modulated output signal provided on the MDOUT

pin can also be inverted. Inverting the modulated out-

put signal is enabled by setting the MDOPOL bit of the

MDCON register.

12.10 Slew Rate Control

When modulated data streams of 20 MHz or greater

are required, the slew rate limitation on the output port

pin can be disabled. The slew rate limitation can be

removed by clearing the MDSLR bit in the MDCON

12.11 Operation In Sleep Mode

The DSM module is not affected by Sleep mode. The

DSM can still operate during Sleep if the Carrier and

Modulator input sources are also still operable during

Sleep.

12.12 Effects of a Reset

Upon any device Reset, the Data Signal Modulator

module is disabled. The user’s firmware is responsible

for initializing the module before enabling the output.

The registers are reset to their default values.

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